Central Processing Unit (CPU) Architecture (Copy)
Cheat Sheet: A Level Computer Science – Computer Architecture, Registers, Buses, and Interrupts
1. Von Neumann Model & Stored Program Concept
- Von Neumann Architecture:
- Single memory for instructions and data
- Executes instructions sequentially unless changed by a control instruction
- Stored Program Concept:
- Instructions are stored in memory
- Fetched and executed one at a time by the processor
2. Registers – Purpose and Types
General-Purpose Registers
- Temporarily hold data or intermediate results during processing
Special-Purpose Registers
| Register | Function |
|---|---|
| Program Counter (PC) | Holds the memory address of the next instruction |
| Memory Address Register (MAR) | Holds address of memory location to be accessed |
| Memory Data Register (MDR) | Temporarily stores data being transferred to/from memory |
| Current Instruction Register (CIR) | Holds the current instruction being executed |
| Accumulator (ACC) | Stores results of ALU operations |
| Index Register (IX) | Used for indexed addressing in arrays/loops |
| Status Register | Stores flags (e.g., zero, carry, overflow) set by ALU operations |
3. Core Components of the CPU
| Component | Function |
|---|---|
| ALU (Arithmetic Logic Unit) | Performs arithmetic and logical operations |
| CU (Control Unit) | Coordinates all operations of the computer |
| System Clock | Regulates timing of all operations |
| IAS (Immediate Access Store) | Main memory storing both data and instructions (RAM) |
4. System Buses
| Bus | Purpose |
|---|---|
| Data Bus | Transfers actual data between components |
| Address Bus | Carries memory addresses of data/instructions |
| Control Bus | Carries control signals (e.g., read/write, interrupt) |
- Bus Width: Number of bits carried at once; wider bus = faster transfer
5. Factors Affecting System Performance
| Factor | Effect |
|---|---|
| Processor Type & Cores | More cores = parallel processing capability |
| Clock Speed | Measured in GHz; higher = more instructions per second |
| Bus Width | Wider bus = more data transferred simultaneously |
| Cache Memory | Faster than RAM; stores frequently used data close to CPU |
6. Ports and Peripheral Connections
| Port | Use |
|---|---|
| USB | Universal connection for peripherals (keyboard, mouse, flash drives) |
| HDMI | High-definition video/audio output (monitors, TVs) |
| VGA | Analog video output for older displays |
7. Fetch-Execute Cycle
Stages:
- Fetch:
MAR ← [PC]
PC ← PC + 1
MDR ← [Memory[MAR]]
CIR ← MDR - Decode:
- Instruction in CIR is decoded by CU
- Execute:
- CU sends signals to relevant components (e.g., ALU, memory, I/O)
Register Transfer Notation (RTN):
- Example for fetch stage:
MAR ← PC
MDR ← [MAR]
CIR ← MDR
PC ← PC + 1
8. Interrupts
Definition:
- A signal indicating an event that needs immediate CPU attention
Causes:
- Hardware failure, I/O requests, timer signals, software errors
Applications:
- Multitasking OS, real-time systems, device drivers
Interrupt Service Routine (ISR):
- Software routine triggered by an interrupt
- Saves current state, handles interrupt, restores state
Interrupt Handling in F-E Cycle:
- Interrupt checked between instructions (after execute, before fetch)
- If interrupt exists:
- CPU pauses current process
- PC and register states saved
- ISR executed
- State restored and process resumes