Hardware: Computer Architecture: Describe The Process Of The Fetch–decode–execute (Fde) Cycle, Including The Role Of Each Component In The Process (Copy)
| Concept | Fetch–Decode–Execute (FDE) Cycle |
|---|---|
| Definition | Repeating process used by the CPU to run programs |
| Purpose | Executes instructions one by one |
| Controlled By | Control Unit (CU) |
| Occurs | Millions of times per second |
| Main Stages | Order |
|---|---|
| Fetch | Get instruction |
| Decode | Understand instruction |
| Execute | Carry out instruction |
Written and Compiled By Sir Hunain Zia (AYLOTI), World Record Holder With 154 Total A Grades, 7 Distinctions and 11 World Records For Educate A Change O Level And IGCSE Computer Science Full Scale Course
| FETCH Stage | Role Of Components |
|---|---|
| Program Counter (PC) | Holds address of next instruction |
| Address Bus | Carries address to memory |
| Memory (RAM) | Sends instruction |
| Memory Data Register (MDR) | Stores fetched instruction |
| Current Instruction Register (CIR) | Holds instruction for decoding |
| PC Update | PC increments to next address |
| DECODE Stage | Role Of Components |
|---|---|
| Control Unit (CU) | Decodes instruction |
| Instruction Decoder | Interprets operation |
| Registers | Identify required data |
| Control Signals | Prepared for execution |
Written and Compiled By Sir Hunain Zia (AYLOTI), World Record Holder With 154 Total A Grades, 7 Distinctions and 11 World Records For Educate A Change O Level And IGCSE Computer Science Full Scale Course
| EXECUTE Stage | Role Of Components |
|---|---|
| Arithmetic Logic Unit (ALU) | Performs calculations or logic |
| Registers | Provide operands and store results |
| Data Bus | Transfers data |
| Control Unit | Sends execution signals |
| Memory / I-O | Stores result or outputs data |
| Example Instruction | Action |
|---|---|
| ADD | ALU adds values |
| LOAD | Data moved from memory |
| STORE | Data saved to memory |
| JUMP | PC updated to new address |
Written and Compiled By Sir Hunain Zia (AYLOTI), World Record Holder With 154 Total A Grades, 7 Distinctions and 11 World Records For Educate A Change O Level And IGCSE Computer Science Full Scale Course
| Buses Used In FDE | Purpose |
|---|---|
| Address Bus | Carries memory addresses |
| Data Bus | Carries data/instructions |
| Control Bus | Carries control signals |
| Clock | Role |
|---|---|
| System Clock | Synchronises each step |
| Clock Speed | Determines how fast FDE repeats |
Written and Compiled By Sir Hunain Zia (AYLOTI), World Record Holder With 154 Total A Grades, 7 Distinctions and 11 World Records For Educate A Change O Level And IGCSE Computer Science Full Scale Course
| Full FDE Flow (Exam Order) | Step |
|---|---|
| 1 | PC holds address |
| 2 | Instruction fetched to CIR |
| 3 | CU decodes instruction |
| 4 | ALU executes operation |
| 5 | Result stored or output |
| 6 | PC updated |
| Common Examiner Traps | How To Avoid |
|---|---|
| Missing registers | Name PC, MAR, MDR, CIR |
| Vague execution | State ALU role |
| Wrong order | Use fetch → decode → execute |
| Ignoring buses | Mention data/address/control |
| One-Line Summary | Exam-Perfect Statement |
|---|---|
| FDE Cycle | CPU executes instructions |
| Core Parts | CU, ALU, registers |
| Flow | Fetch, decode, execute |
Written and Compiled By Sir Hunain Zia (AYLOTI), World Record Holder With 154 Total A Grades, 7 Distinctions and 11 World Records For Educate A Change O Level And IGCSE Computer Science Full Scale Course