Hardware: Computer Architecture: Understand The Purpose Of The Components In A Cpu, In A Computer That Has A Von Neumann Architecture (Copy)
| Concept | Von Neumann Architecture |
|---|---|
| Definition | Computer architecture where data and instructions share the same memory |
| Key Feature | Single memory and single bus |
| Used In | Most general-purpose computers |
| CPU Components | Purpose |
|---|---|
| Control Unit (CU) | Controls and coordinates operations |
| Arithmetic Logic Unit (ALU) | Performs calculations and logic |
| Registers | Fast temporary storage inside CPU |
| System Clock | Synchronises CPU operations |
| Buses | Transfer data, instructions, addresses |
Written and Compiled By Sir Hunain Zia (AYLOTI), World Record Holder With 154 Total A Grades, 7 Distinctions and 11 World Records For Educate A Change O Level And IGCSE Computer Science Full Scale Course
| Control Unit (CU) | Purpose |
|---|---|
| Instruction Control | Manages execution sequence |
| Signal Generation | Sends control signals |
| Coordination | Controls data flow between CPU, memory, I/O |
| Fetch–Decode | Fetches and decodes instructions |
| Arithmetic Logic Unit (ALU) | Purpose |
|---|---|
| Arithmetic Operations | Add, subtract, multiply, divide |
| Logical Operations | AND, OR, NOT |
| Comparisons | Equal, greater, less |
| Registers | Purpose |
|---|---|
| Definition | Very fast memory inside CPU |
| Role | Holds data, instructions, addresses |
| Speed | Faster than RAM |
Written and Compiled By Sir Hunain Zia (AYLOTI), World Record Holder With 154 Total A Grades, 7 Distinctions and 11 World Records For Educate A Change O Level And IGCSE Computer Science Full Scale Course
| Key Registers | Purpose |
|---|---|
| Program Counter (PC) | Address of next instruction |
| Memory Address Register (MAR) | Holds memory address |
| Memory Data Register (MDR) | Holds data from memory |
| Accumulator (ACC) | Stores ALU results |
| Current Instruction Register (CIR) | Holds current instruction |
| System Clock | Purpose |
|---|---|
| Synchronisation | Controls timing of operations |
| Speed Control | Determines CPU speed |
| Coordination | Keeps components in step |
| Buses | Purpose |
|---|---|
| Address Bus | Carries memory addresses |
| Data Bus | Carries data and instructions |
| Control Bus | Carries control signals |
Written and Compiled By Sir Hunain Zia (AYLOTI), World Record Holder With 154 Total A Grades, 7 Distinctions and 11 World Records For Educate A Change O Level And IGCSE Computer Science Full Scale Course
| Von Neumann Feature | Effect |
|---|---|
| Single Memory | Stores data and instructions together |
| Single Bus | Data and instructions share path |
| Bottleneck | Limits performance (Von Neumann bottleneck) |
| Von Neumann Bottleneck | Explanation |
|---|---|
| Cause | One bus for data and instructions |
| Effect | CPU waits for memory access |
| Result | Reduced performance |
| Examiner Keywords | Use These |
|---|---|
| Shared memory | Core feature |
| Fetch–decode–execute | CPU operation |
| Registers | Fast internal storage |
| Bottleneck | Performance limit |
Written and Compiled By Sir Hunain Zia (AYLOTI), World Record Holder With 154 Total A Grades, 7 Distinctions and 11 World Records For Educate A Change O Level And IGCSE Computer Science Full Scale Course
| Common Examiner Traps | How To Avoid |
|---|---|
| Mixing Harvard & Von Neumann | Emphasise shared memory |
| Forgetting registers | Name key ones |
| Ignoring buses | Include all three |
| Vague purposes | State clear functions |
| One-Line Summary | Exam-Perfect Statement |
|---|---|
| Von Neumann CPU | Uses shared memory |
| Components | CU, ALU, registers, buses |
| Limitation | Von Neumann bottleneck |
Written and Compiled By Sir Hunain Zia (AYLOTI), World Record Holder With 154 Total A Grades, 7 Distinctions and 11 World Records For Educate A Change O Level And IGCSE Computer Science Full Scale Course